Top gate TFT structure having light shielding layer and method to fabricate the same
US6608658B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2000 |
| Grant date | Aug 19, 2003 |
| Priority date | — |
| Expiry date | Apr 4, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/1362
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The present invention provides a method of fabricating a TFT structure by two masking processes. More specifically, a light shielding layer and an interlayer insulating layer are sequentially formed on a substrate, and then source/drain electrodes are formed on the interlayer insulating layer (a first masking step). A semiconductor layer, a gate insulating layer and a gate metal layer are sequentially formed so as to cover the source/drain electrodes, and a gate electrode is formed in a second masking step. Subsequently, the gate insulating layer and the semiconductor layer are etched, and the interlayer insulating layer and the light shielding layer, which are disposed under the source/drain electrodes, are etched using the source/drain electrodes as a mask, thus obtaining a top gate TFT structure. When the interlayer insulating layer and the gate insulating layer are made of an insulating material containing SiOX and SiNX as a main component, the gate insulating layer and the semiconductor layer are naturally over-etched more than the interlayer insulating layer and the light shielding layer by plasma-etching with mixed gas of CF4 and hydrogen, thus obtaining a TFT structure with…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.