Compact high addressability rendering
US6608701B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 1999 |
| Grant date | Aug 19, 2003 |
| Priority date | — |
| Expiry date | Jul 7, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N1/4056
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A compact rendering processor for processing image data including a multi-bit halftone region generates high addressability pixels. The compact rendering processor includes a tagging sub-processor operating on the image data to identify a target pixel and a neighboring pixel to determine a fill-order. The compact rendering processor also includes a rendering sub-processor that converts the target pixel into a high addressability pixel based upon the fill-order. Optionally, a diffusion sub-processor can be included to diffuse an error resulting from the conversion of the target pixel into a high addressability pixel to other pixels within the image data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.