Two-dimensional execution queue for host adapters
US6609161B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 1, 2000 |
| Grant date | Aug 19, 2003 |
| Priority date | — |
| Expiry date | Jun 30, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A two-dimensional hardware control block execution queue facilitates multiple command delivery to a single target device over an I/O bus, such as a SCSI bus. The two-dimensional hardware control block execution queue includes a plurality of target queues where each target queue includes at least one hardware control block. Each of target queues is a queue of hardware command blocks, e.g., SCSI control blocks (SCBs) for a specific target device on the I/O bus. There is only one target queue for each target device. One head hardware control block, and only one head hardware control block of each target queue, is included in a common queue. When a selection is made by a host adapter for a target device based upon a hardware control block addressed by a head pointer to the common queue, all hardware control blocks in the target queue within the two-dimensional hardware control block queue, which are accepted by the target device, are transferred to the target device. If there are more hardware control blocks in the target queue than are accepted by the target device, the target queue is moved to the end of two-dimensional queue, and a common queue tail pointer is changed to address the…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.