Method and apparatus for reducing the power consumed by a processor by gating the clock signal to pipeline stages
US6609209B1 · kind B1 · utility
40Cited by
3References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 1999 |
| Grant date | Aug 19, 2003 |
| Priority date | — |
| Expiry date | Dec 29, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a pipeline having first and second stages and a shift register having first and second latches. An interface circuit is used to provide a clock signal from a clock signal line to the first and second stages based, at least in part, on first and second bits to be stored in the first and second latches, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.