Utilization-based power management of a clocked device
US6609211B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 20, 2002 |
| Grant date | Aug 19, 2003 |
| Priority date | — |
| Expiry date | Aug 20, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A battery powered computer system determines when the system is not in use by monitoring various events associated with the operation of the system. The system preferably monitors the number of cache read misses and write operations, i.e., the cache hit rate, and reduces the system clock frequency when the cache hit rate rises above a certain level. When the cache hit rate is above a certain level, then it can be assumed that the processor is executing a tight loop, such as when the processor is waiting for a key to be pressed and then the frequency can be reduced without affecting system performance. Alternatively, the apparatus monitors the occurrence of memory page misses, I/O write cycles or other events to determine the level of activity of the computer system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.