Ordering binary decision diagrams used in the formal equivalence verification of digital designs
US6609234B2 · kind B2 · utility
4Cited by
7References
24Claims
0Family size
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Key dates
| Filing date | Jun 29, 2001 |
| Grant date | Aug 19, 2003 |
| Priority date | — |
| Expiry date | Jun 29, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for ordering input variables in binary decision diagrams is described. Once a plurality of disjoint sets of input variables can be found from the sub-equations of a Boolean function, an initial top-level order can be used to form a significantly smaller diagram. The diagram can by reduced further by application of the method recursively on the sub-equations and successive sub-equations until primary inputs are reached.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.