Method for providing a fill pattern for an integrated circuit design
US6609235B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2001 |
| Grant date | Aug 19, 2003 |
| Priority date | — |
| Expiry date | Oct 17, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for providing a fill pattern for integrated circuit designs is disclosed. A keepout file having keepout data is generated from a chip design layout file having chip design layout data. The keepout file includes a map of areas of an integrated circuit design where fill patterns cannot be placed. The map of areas from the keepout file is then overlaid with a fill pattern to yield a fill-pattern file. Fill patterns from the fill-pattern file is removed from locations that coincide with locations as defined by the keepout data to yield a final-fill file with crucial fill pattern data. The crucial fill pattern data from the final-fill file is overlaid on the design layout data in the chip design layout file to yield a complete design layout file. Finally, the design rule integrity and logical to physical correspondence of the complete design layout file is verified.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.