Vertical component peripheral structure
US6611006B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 15, 2001 |
| Grant date | Aug 26, 2003 |
| Priority date | — |
| Expiry date | May 15, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/206
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A power component formed in an N-type silicon substrate, the lower and upper surfaces of which respectively include a first and a second P-type region that do not extend to the component periphery, a high voltage being capable of existing between the first and second regions and having to be withstood by the junctions between the first and second regions and the substrate. A deep insulating region that does not join the first region is provided at the lower periphery of the component, the lower surface of the substrate between said deep insulating region and the first region being coated with an insulating layer, the height of the deep insulating region being greater than that of a possible soldering upward extension formed during the soldering of the lower surface on a heat sink.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.