Apparatus and method for synchronizing multiple circuits clocked at a divided phase locked loop frequency
US6611159B1 · kind B1 · utility
2Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2002 |
| Grant date | Aug 26, 2003 |
| Priority date | — |
| Expiry date | Feb 28, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/095
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for synchronizing multiple circuits or chips clocked at a divided phase lock loop (PLL) frequency. The apparatus generally includes a plurality of chips, each chip including a phase locked loop (PLL) and a circuit for generating a system clock signal, a circuit for receiving the lock signal from each PLL and for generating an All-Locked signal in response to all of the PLLs achieving lock, and a synchronizing circuit for synchronizing the system clocks of the plurality of chips upon receipt of the All-Locked signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.