Switched capacitor scheme for offset compensated comparators
US6611163B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2002 |
| Grant date | Aug 26, 2003 |
| Priority date | — |
| Expiry date | Mar 20, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R19/0023
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An offset compensated comparator 70 has capacitors 80 and 81 coupled directly between the inputs of a preamplifier 78 and the outputs of a previous stage amplifier 62. The comparator 70 also includes additional capacitors 82 and 83 coupled between the inputs of the preamplifier 78 and reference voltage nodes VREFP and VREFM. Switches 73 and 74 are coupled between the additional capacitors 82 and 83 and the reference voltage nodes VREFP and VREFM. An additional switch 72 is coupled between the additional capacitors 82 and 83. In this configuration, there are no series sampling switches between the previous stage amplifier 62 and the comparator 70. Eliminating the series switches reduces the load seen by the previous stage amplifier 62, which allows the previous stage amplifier 62 to have a faster settling time. This allows the current in the previous stage amplifier 62 to be decreased which reduces the power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.