Initialization system for recovering bits and group of bits from a communications channel
US6611217B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2002 |
| Grant date | Aug 26, 2003 |
| Priority date | — |
| Expiry date | May 17, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/046
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system normally converts a parallel data word to a single serial data stream to use a high speed serial link. The parallel data word is partitioned into N sub-sets or nibbles and each nibble is then serialized and transmitted over N serial links using high speed differential drivers. Each of the N serialized nibbles are received in a differential receiver. The serialized nibbles are then coverted back into N parallel nibbles and the N parallel nibbles are then assembled back to the original parallel data word. To increase reliability, the received data is coupled to a tapped delay element having M stages of delay. A training sequence and algorithm are used to determine which of the taps of the delay element are a desired delay distance away from data transitions. These taps are then used to sample the incoming signals to reconstruct the parallel data word.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.