Packet switching apparatus with a common buffer
US6611527B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2000 |
| Grant date | Aug 26, 2003 |
| Priority date | — |
| Expiry date | Feb 3, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5684
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A plurality of address chains are assigned to each of such flows as output lines, priority control, etc. in the address management carried out in a switch with a shared buffer. Each of the address chains has a write address register 20 and a read address register 30. The switch is also provided with a distributive pointer 22 for distributing cells in a flow to a plurality of address chains and a write address register selector 21, as well as a read pointer 32 for reading packets from a plurality of the address chains and a read address register selector 31 so as to read the packets through a pipeline with use of those plural address chains.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.