Flexible and efficient channelizer architecture
US6611855B1 · kind B1 · utility
11Cited by
12References
31Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 21, 1999 |
| Grant date | Aug 26, 2003 |
| Priority date | — |
| Expiry date | Jun 21, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04W88/08
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A digital channelizer/de-channelizer architecture that, with a minimum amount of hardware, is capable of dynamically adapting to changing system requirements. Preferably, the digital channelizer/de-channelizer, which is applied with a modified fast convolution algorithm, includes a plurality of dedicated, optimized, pipeline modules that may be dynamically adjusted for allocating and handling different bandwidths, a flexible number of channels, and simultaneous multiple standards.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.