Control system for high speed rule processors
US6611875B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1999 |
| Grant date | Aug 26, 2003 |
| Priority date | — |
| Expiry date | Apr 30, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/50
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A control system for high-speed rule processors used in a gateway system is disclosed. The gateway system employing the current invention can process packets at wire speed by using massive parallel processors, each of the processors operating concurrently and independently. Further, the processing capacities in the gateway system employing the current invention are expandable. The number of packet inspector engines may be increased and all of the engines are connected in a cascade manner. Under the control system, all of the engines operate concurrently and independently and results from each of the engines are collected sequentially through a common data bus. As such the processing speed of packets becomes relatively independent of the complexities and numbers of rules that may be applied to the packets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.