Memory interface with programable clock to output time based on wide range of receiver loads
US6611905B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2000 |
| Grant date | Aug 26, 2003 |
| Priority date | — |
| Expiry date | Oct 9, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4239
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system, and a method of operating a data processing system. The data processing system comprises a clock generator for generating a system clock signal, and a memory unit having a plurality of memory modules for storing data. The data processing system further comprises a memory controller coupled to the clock generator for receiving the system clock signal therefrom, and coupled to the memory modules for outputting memory address and control signals to said modules. The memory controller is programmable to have different clock-to-output delays, on signals from the memory controller end, based on the memory installed in the system. Preferably, the memory controller includes means for generating a series of memory address and control signals in response to receiving the system clock signal, and for outputting the memory address and control signals to the memory modules; and programmable means for determining time delays between the time the memory controller receives the system clock signal and the time the memory means outputs the memory address and control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.