Mechanisms to sample shared-dirty-line addresses
US6611926B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 1999 |
| Grant date | Aug 26, 2003 |
| Priority date | — |
| Expiry date | Nov 29, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device and method for collecting data on which lines are being shared in a multiprocessor system having cache memories is described. In the present invention, a sample arm register observes a local channel, such as a bus, for key events. Upon waiting a certain number of events, the sample arm register arms a sample register. Once armed the sample register will latch the next qualified address of the data being collected. The sampled data is then stored in memory. Post processing software will read the data from memory. The samples are then analyzed to correlate them with such things as locations and data structures in the system. This helps dynamically optimize the work load to reduce shared dirty line traffic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.