Method of fabricating semiconductor device having element isolation trench
US6613635B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2001 |
| Grant date | Sep 2, 2003 |
| Priority date | — |
| Expiry date | Dec 17, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0188
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Threshold voltage fluctuation in upper corner portions of a trench isolation is inhibited by rounding upper corner portions of the trench by thermal oxidation, introducing a first impurity into both upper corner portions of the trench and heat-treating the semiconductor substrate. Embodiments include increasing the threshold voltage in the upper corner portion of the trench in an n-channel transistor, previously increased by rounding oxidation, and introducing a p-type impurity, thereby canceling the threshold voltage reduction resulting from diffusion of the impurity during heat-treating the semiconductor substrate. In a p-channel transistor, the threshold voltage in the upper corner portion of the trench is increased by rounding oxidation thereby canceling the threshold voltage reduction resulting from introduction of the p-type first impurity into both upper corner portions of the trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.