Failsafe interface circuit with extended drain devices
US6614262B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2002 |
| Grant date | Sep 2, 2003 |
| Priority date | — |
| Expiry date | Apr 5, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Failsafe interface circuits are provided for an integrated circuit having a core logic section providing a signal to, or receiving a signal from, a bond pad connection. The interface circuits employ high voltage tolerant, extended drain devices in circuit arrangements which insure that the stress of a failsafe event is only exhibited by the extended drain devices. A failsafe event is defined as a bond pad voltage which exceeds the supply voltage of the integrated circuit plus the threshold voltage of the transistors within the integrated circuit. Both failsafe output driver circuit and failsafe receiver circuit embodiments are provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.