Low voltage, high speed CMOS CML latch and MUX devices
US6614291B1 · kind B1 · utility
7Cited by
5References
6Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 15, 2001 |
| Grant date | Sep 2, 2003 |
| Priority date | — |
| Expiry date | Jun 15, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0036
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A signal multiplexer system and a signal latch system for low voltage (Vdd≈1.2 volts) and high speed transitions between states. A dc signal isolation circuit, inserted between a clock signal circuit and a signal input/output circuit, allows use of a two-transistor-layer vertical structure that provides adequate headroom voltage (about 0.3-0.4 volts, or larger) for high speed transistor response.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.