Differential amplifier offset adjustment
US6614301B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2002 |
| Grant date | Sep 2, 2003 |
| Priority date | — |
| Expiry date | Jan 31, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0018
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A differential amplifier includes a source coupled differential pair of transistors. A feedback loop detects the presence of an input referred offset in the differential amplifier and modifies a body bias voltage on at least one of the transistors in the differential pair. A comparator detects a differential output voltage when the differential input voltage is set to zero. In some embodiments, a charge pump in the feedback loop injects charge on the body of the transistor to modify the bias voltage. In other embodiments, a digital-to-analog converter receives a digital control word and produces a bias voltage on the body of the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.