Semiconductor memory device and data read method thereof
US6614710B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2001 |
| Grant date | Sep 2, 2003 |
| Priority date | — |
| Expiry date | Nov 9, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a semiconductor memory device and a data read method thereof. The semiconductor memory device comprises a memory cell array comprising a plurality of sub-arrays, said sub-arrays comprising a plurality of memory cells and repeaters, wherein each of said memory cells is connected to a corresponding pair of read word lines, a corresponding pair of read bitlines, a corresponding pair of write word lines, and a corresponding pair of write bitlines, and wherein each of said repeaters is connected to said corresponding pair of read bitlines of each said memory cell and a corresponding pair of common main read bitlines so as to transmit read data from said corresponding pair of read bitlines to said corresponding pair of common main read bitlines in response to an applied enable control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.