Patent · US Expired

Asynchronous FIFO increment and decrement control for interfaces that operate at differing clock frequencies

US6614798B1 · kind B1 · utility

8Cited by
5References
5Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMar 30, 1999
Grant dateSep 2, 2003
Priority date—
Expiry dateMar 30, 2019

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH04L2012/5674
  • WIPO fieldDigital communication
  • WIPO sectorElectrical engineering

Abstract

A First-In-First-Out (FIFO) memory device includes a FIFO memory block, a data input interface that writes data into the FIFO memory block in synchronization with a first clock, and a data output interface that reads the data from the FIFO memory block in synchronization with a second clock. The data input interface provides a first indication to the data output interface that the received data has been written into the FIFO memory block. The first indication persists until reset by the data output interface. The data output interface provides a second indication to the data input interface that the received data has been read from the FIFO memory block. The second indication persists until reset by the data input interface.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.