Signal processing apparatus
US6614841B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 24, 2000 |
| Grant date | Sep 2, 2003 |
| Priority date | — |
| Expiry date | Mar 24, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/41
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A reproduced signal is adaptively equalized in an adaptive equalizer after going through an AD converter. The AD converter, the adaptive equalizer, a phase error detector, a phase shifter, a DA converter, a loop filter, and a variable frequency oscillation circuit, all of which structure a PLL circuit, and a clock signal phase-locked to reproduced data is fed back to the AD converter. The phase shifter slightly shifts, as appropriate, a phase error detected in the phase detector according to the change in a barycenter of tap coefficients detected in a tap barycenter detection circuit. With such structure, signals can be processed in an accurate manner without causing competition in operation between the PLL and adaptive equalization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.