Intermediary frequency input QPSK demodulator
US6614856B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 28, 1999 |
| Grant date | Sep 2, 2003 |
| Priority date | — |
| Expiry date | Jun 28, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/22
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a demodulator provided to extract two signals modulated in phase quadrature from an intermediary frequency signal, including two analog-to-digital converters receiving the intermediary frequency signal and clocked in phase opposition by a clock at a frequency smaller than the intermediary frequency, at least equal to the bandwidth of the modulated signals, and such that the central frequency of one of the aliased spectrums of the signal converted into digital is substantially equal to half the clock frequency; and two multipliers respectively receiving the outputs of the analog-to-digital converters and receiving at the same time a sequence of values 1, −1, 1, −1, 1 . . . at the clock rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.