Bit synchronization method and bit synchronization device
US6614863B1 · kind B1 · utility
2Cited by
4References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 7, 1999 |
| Grant date | Sep 2, 2003 |
| Priority date | — |
| Expiry date | Dec 7, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/091
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A bit synchronization device which extracts an output data signal and an output clock signal from an input data signal on the basis of a multi-phase clock signal. The bit synchronization device is provided with a processing circuit which holds a phase corresponding to a change point of an input data signal with a multi-phase clock signal, and while the input data has a phase without change point, carrying out a data identification free from an error by selecting a clock signal corresponds to the phase without change point.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.