Method and apparatus for concatenating bits of odd-length words
US6614934B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2000 |
| Grant date | Sep 2, 2003 |
| Priority date | — |
| Expiry date | Mar 27, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/70
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for concatenating data words from a bitstream includes a scratch memory (802, 902) containing last words of unfinished blocks and left-aligned extra data words of finished blocks. A previous register (808, 908) holds one last word of an unfinished block. A next register (806, 906) holds a first of possibly many extra data words associated with the last word. A bit detector (810, 910), coupled to the previous register (808, 908) and the next register (806, 906), first concatenates the last word and the first extra data word and identifies selected bits for the detection of a valid code word. When no more valid code words can be found from the selected bits, and more data associated with the unfinished block exists, the first extra data word is moved to the previous register (808, 908) and a second extra data word is moved to the next register (806, 906). The first extra data word and the second extra data word are concatenated for the detection of another valid code word. In various embodiments of the present invention, a start bit register (814, 914) and a remaining bits register (816) hold values that are used in concatenation and the detection of valid code…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.