Selection based rounding system and method for floating point operations
US6615228B1 · kind B1 · utility
4Cited by
6References
19Claims
0Family size
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Key dates
| Filing date | May 30, 2000 |
| Grant date | Sep 2, 2003 |
| Priority date | — |
| Expiry date | Oct 7, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49957
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A selection based rounding system and method eliminate the need for post increment based rounding in a floating point (FP) fused multiply adder that can be utilized in a processor or other digital circuit to significantly increase speed. Generally, an unincremented result and an incremented result are produced in parallel and then either one is selected as a rounded result based upon specified rounding criteria, thereby eliminating the time consuming need for an incrementor to perform rounding at or near the end of the FP fused multiply adder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.