Fast look-up of indirect branch destination in a dynamic translation system
US6615300B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2000 |
| Grant date | Sep 2, 2003 |
| Priority date | — |
| Expiry date | Jul 12, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Dynamic translation of indirect branch instructions of a target application by a host processor is enhanced by including a cache to provide access to the addresses of the most frequently used translations of a host computer, minimizing the need to access the translation buffer. Each entry in the cache includes a host instruction address, a logical address of the instruction of the target application, the physical address of that instruction, the code segment limit to the instruction, and the context value of the host processor associated with that instruction, the last four named components constituting tags to the host instruction address, and a valid-invalid bit. In a basic embodiment, the cache is a software cache apportioned by software from the main processor memory chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.