Microprocessor with dual execution core operable in high reliability mode
US6615366B1 · kind B1 · utility
99Cited by
10References
24Claims
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Key dates
| Filing date | Dec 21, 1999 |
| Grant date | Sep 2, 2003 |
| Priority date | — |
| Expiry date | Dec 21, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/845
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor is provided having dual execution cores that may be switched between high reliability and high performance execution modes dynamically, according to the type of code segment to be executed. When the processor is in high performance mode, the dual execution cores operate in lock step on identical instructions, and the execution results generated by each execution core are compared to detect any errors. In high performance monde, the dual execution cores operate independently.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.