Robust bit scheme for a memory of a replaceable printer component
US6616260B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2001 |
| Grant date | Sep 9, 2003 |
| Priority date | — |
| Expiry date | May 25, 2021 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB41J2/17546
- WIPO fieldTextile and paper machines
- WIPO sectorMechanical engineering
Abstract
A system and method for detecting an error in data received from a memory of a replaceable printer component includes providing a first parity bit associated with a first data item. The first data item and the first parity bit are stored in the memory. The printer includes a plurality of electrically conductive lines. The memory includes a plurality of bits. At least one of the electrically conductive lines is associated with each bit. The first data item and the first parity bit are read from the memory. An electrical test of at least one of the electrically conductive lines is performed. An error in the first data item is identified based on the first parity bit read from the memory and the electrical test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.