Routing for multilayer ceramic substrates to reduce excessive via depth
US6617243B1 · kind B1 · utility
10Cited by
7References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 10, 2000 |
| Grant date | Sep 9, 2003 |
| Priority date | — |
| Expiry date | Aug 10, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49126
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Aspects for routing in multilayer ceramic substrates that reduces via depth and avoids via bulge are described. The aspects include providing a multilayer ceramic substrate with at least two redistribution layers. Vias for each of a plurality of signal lines are jogged on at least a second redistribution layer of the at least two redistribution layers. Further, the aspects include providing the second redistribution layer no more than seven layers deep in the multilayer ceramic substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.