Stress relief bend useful in an integrated circuit redistribution patch
US6617510B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2001 |
| Grant date | Sep 9, 2003 |
| Priority date | — |
| Expiry date | Sep 18, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10757
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A metallic or an electrical trace having a terminus and a stress relief bend formed in the trace adjacent the terminus. The electrical trace may have a portion carried by a flexible substrate to form a flexible circuit. The stress relief bend may be free floating and extend from the flexible substrate or may be encapsulated by the flexible substrate. The electrical circuit and the flexible circuit each have a generally planar portion extending in the X and Y axis, with the stress relief bend projecting into the Z axis. This allows electrical traces to be spaced with a very narrow pitch because the stress relief bend does not consume any valuable real estate on the flexible circuit or the substrate to which the electrical trace is applied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.