Packaged integrated circuit and method therefor
US6617524B2 · kind B2 · utility
4Cited by
5References
25Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 11, 2001 |
| Grant date | Sep 9, 2003 |
| Priority date | — |
| Expiry date | Dec 11, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/49171
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
To mitigate mold encapsulant bleeding and solder mask cracking in plastic semiconductor packages, a damming structure constructed from metal traces is formed in-line with the encapsulant perimeter. In one embodiment, each damming trace is connected to only one electrical trace, which includes a bonding connection, a signal portion and a plating portion. The damming traces can consist of one trace that is wider than any of the signal traces or multiple rows of traces, for example. The result is a reduction in mold encapsulant bleeding and, thus, an eradication of the processes performed to clean the bleeding.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.