Analog pre-processor with improved input common mode range
US6617567B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2001 |
| Grant date | Sep 9, 2003 |
| Priority date | — |
| Expiry date | Jul 25, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45726
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An analog circuit 20 includes an amplifier 30 with a positive input node, a negative input node, a positive output node and a negative output node. A first capacitor 32 is coupled between the negative input node and an analog signal node. A second capacitor 34 is coupled between the positive input node and a reference voltage node. In addition, a third capacitor 36 is coupled between the positive input node and the negative output node and a fourth capacitor 38 is coupled between the negative input node and the positive output node. A first switch 40 is coupled between the third capacitor 36 and the negative output node and a second switch 42 is coupled between the fourth capacitor 38 and the positive output node. An inverter coupled to the analog signal node drives common mode capacitors coupled between the output of the inverter and the respective negative and positive input nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.