Reduced substrate capacitance high performance SOI process
US6617646B2 · kind B2 · utility
8Cited by
7References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 6, 2002 |
| Grant date | Sep 9, 2003 |
| Priority date | — |
| Expiry date | May 6, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/977
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A silicon on insulator substrate is provided to include the following: a handle wafer; a layer of bonding material; a device wafer, the device wafer including at least one buried impurity region extending from the layer of bonding material upward into the device wafer; and an epitaxial silicon layer provided on a second surface of the device wafer. The silicon on insulator substrate with this configuration can be made with a minimal possible thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.