Semiconductor device with sidewall spacers and elevated source/drain region

US6617654B2 · kind B2 · utility

Assignee

• Mitsubishi Electric Corporation · JP

Inventors

• Toshiyuki Oishi · Tokyo, JP
• Kohei Sugihara · Tokyo, JP
• Naruhisa Miura · Tokyo, JP
• Yuji Abe · Kasai, JP
• Yasunori Tokuda · Tokyo, JP

Key dates

• Filing date: Sep 19, 2001
• Grant date: Sep 9, 2003
• Expiry date: Oct 6, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/021

Abstract

Source and drain regions include regions of an epitaxial silicon film on the surface of the substrate and regions in the substrate. The depth of junctions of the source and drain regions is identical to or shallower than the depth of junctions of extension regions. As a result, even if the thickness of the side wall layer is reduced, since the depletion layer of the extension regions with lower impurity concentration compared with the source and drain regions is predominant, the short channel effect has a smaller effect.