Complementary signal generation circuit
US6617896B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2002 |
| Grant date | Sep 9, 2003 |
| Priority date | — |
| Expiry date | Jun 5, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356113
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is a complementary signal generation circuit that can suppress the distortion of an eye pattern due to a change in signal delay caused by jitter or a change in the rise and fall of a signal caused by a manufacturing factor. An inverter 11 inverts an input signal 101 and generates a first internal signal 104, and an inverter 12 inverts the first internal signal 104 and generates a second internal signal 105. When the first internal signal 104 goes high, a flip-flop 1 reduces the level of an in-phase signal 103 to low, and increases the level of an antiphase signal 102 to high. Thus, when the fall of the in-phase signal is delayed, the flip-flop also delays the rise of the antiphase signal and suppresses the distortion of the eye pattern. And when the ON resistances of transistors Qn1 and Qn2 are changed due to a manufacturing factor, RC series circuits 2 and 3 suppress the change in the driving capability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.