System and method for threshold bias offset voltage cancellation in a comparator
US6617905B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2002 |
| Grant date | Sep 9, 2003 |
| Priority date | — |
| Expiry date | Oct 29, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/2418
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method are provided for reducing the threshold bias offset voltage in a comparator, by canceling and bypassing the bias offset current errors. The comparator system comprises amplification stages with bias cancellation circuitry and a threshold setting circuit. The bias offset current cancellation circuit is used to cancel the base current of differential amplifier input emitter follower. The bias offset current cancellation circuit also cancels the loading effect of amplifier input emitter-follower driving stage. The threshold offset voltage is further reduced by the threshold setting circuit. The threshold-setting circuit includes two integrators and a unit gain operation amplifier. The integrators have the input accept a single-ended input signal, an output connected to the negative input of the comparator, and an output connected to the unit gain operational amplifier, whose output is connected to the negative input of the comparator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.