Mismatch-independent reset sensing for CMOS area array sensors
US6618083B1 · kind B1 · utility
67Cited by
10References
5Claims
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Key dates
| Filing date | Dec 30, 1998 |
| Grant date | Sep 9, 2003 |
| Priority date | — |
| Expiry date | Dec 30, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/77
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Two methods for suppressing the fixed pattern noise effects of a pixel reset switch by ensuring that the reset NMOS device operates in its linear region. The first approach uses a separate reset switch supply voltage, VRES, set to at least one threshold voltage below the sensing switch supply voltage, Vdd. The second approach uses a charge pump and level shifter to push the reset gate voltage at least one threshold voltage higher than a supply voltage common to both the reset and sense transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.