Method for high-density, low-via-count, decoupling capacitor placement
US6618266B2 · kind B2 · utility
9Cited by
4References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2001 |
| Grant date | Sep 9, 2003 |
| Priority date | — |
| Expiry date | Mar 6, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A capacitor mounting method and resulting printed circuit board that increases the mounting density of both vias and decoupling capacitors is presented. Vias are shared between capacitors mounted on the top and bottom of the printed circuit board. This arrangement allows increased decoupling capacitor density and avoids the current doubling problem when shared vias are connected with capacitors installed on the same side of the board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.