Method and apparatus for adjusting control circuit pull-up margin for content addressable memory (CAM)
US6618279B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2001 |
| Grant date | Sep 9, 2003 |
| Priority date | — |
| Expiry date | Aug 6, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for determining a desired operating impedance for a computer memory circuit includes applying, to a reference circuit, a test impedance value to a reference circuit. The test impedance value is controlled by a binary count. A determination is made, based upon the applied test impedance value, whether the reference circuit is in either a first state or a second state. The binary count is incremented if the reference circuit is in the first state and decremented if the reference circuit is in the second state. A condition is determined in which the reference circuit oscillates between the first state and said second state, and a pair of binary count values is stored. The desired operating impedance for the computer memory circuit corresponds to the lower of the stored pair of binary count values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.