Modular memory structure having adaptable redundancy circuitry
US6618301B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 21, 2001 |
| Grant date | Sep 9, 2003 |
| Priority date | — |
| Expiry date | Nov 21, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/808
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides a modular memory structure having adaptable redundancy circuitry, which can repair different types of defects using an addressing line and an enabled line, thereby increasing the yield of the memory device. The modular memory structure having adaptable redundancy circuitry includes: a plurality of main memory blocks to store data; a plurality of redundancy memory blocks to replace the defective memory blocks; a plurality of fuse sets to generate replacement signals by programming the plurality of fuse sets to replace the defect memory positions on the main memory blocks with the corresponding redundancy memory blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.