Method and architecture for reducing the power consumption for memory devices in refresh operations
US6618314B1 · kind B1 · utility
35Cited by
24References
24Claims
0Family size
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Key dates
| Filing date | Mar 4, 2002 |
| Grant date | Sep 9, 2003 |
| Priority date | — |
| Expiry date | Mar 4, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for reducing power consumption during background operations in a memory array with a plurality of sections comprising the steps of (i) enabling the background operations in one or more sections of the memory array when one or more control signals are in a first state and disabling the background operations in one or more sections of the memory array when the one or more control signals are in a second state and (ii) generating the one or more control signals in response to an address signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.