Semiconductor memory device
US6618320B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2002 |
| Grant date | Sep 9, 2003 |
| Priority date | — |
| Expiry date | Dec 11, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device is provided with a clock generation circuit that generates a first clock that has the same frequency and phase as an external clock, and a second clock that has the same frequency as the external clock but a phase a quarter phase shifted, and the first clock and the second clock are supplied to the two DDR-DRAMs as clocks so that the two DDR-DRAMs can operate in a state of being a quarter phase shifted from each other. A data output section outputs data respectively for time periods corresponding to a quarter phase from points a fixed phase behind the leading edge and the trailing edge of the first or the second clock and brings a data output circuit into a high impedance state for other time periods.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.