Procedure and processor arrangement for parallel data processing

US6618800B1 · kind B1 · utility

Assignee

• Systemonic AG · DE

Inventors

• Matthias Weiss · Hilchenbach, DE
• Gerhard Fettweis · Dresden, DE

Key dates

• Filing date: Jan 18, 2000
• Grant date: Sep 9, 2003
• Expiry date: Jan 18, 2020

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F13/1663
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A procedure and a processor arrangement for parallel data processing in which data are read out from a data memory and are conveyed via a communications unit to processing units for parallel processing. The data are divided into data groups with several elements and are stored in a group memory under a common address. To each data group, a processing unit is allocated, in that at least one element of a data group can be directly linked to the allocated processing unit, directly bypassing the communications unit. In a parallel fashion, a data group is read out from the data memory and is distributed over one or several processing units and is processed in a parallel fashion in the latter.