Method and bus interface employing a memory in an intergrated circuit which is used to link a bus with an application device to be controlled by the bus

US6618832B1 · kind B1 · utility

Assignee

• Thomson Licensing · FR

Inventors

• Siegfried Schweidler · Gehrden, DE
• Thomas Brune · Hannover, DE

Key dates

• Filing date: Feb 29, 2000
• Grant date: Sep 9, 2003
• Expiry date: Feb 29, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H04L49/9089
• WIPO field: Digital communication
• WIPO sector: Electrical engineering

Abstract

The IEEE1394 bus communication protocol has three layers: physical layer, link layer, and transaction layer. A link layer IC implements the interface to an external application and prepares data for sending on the bus, or interprets incoming data packets from the IEEE1394 bus. A physical layer IC implements the direct electrical connection to the bus and controls many functions including arbitration for sending data on the bus. According to the invention the capacity of the on-chip memory becomes assigned in a flexible way in order to be able to meet the requirements for any specific service. Further, the on-chip memory is prevented from storing data packets containing transmission errors by CRC checking on the fly header data and other data. This is performed for asynchronous data packets as well as isochronous data packets, and allows to have a minimum on-chip memory capacity only.