Method and apparatus for the use of embedded resistance to linearize and improve the matching properties of transistors
US6621146B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 26, 2001 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Dec 17, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
An integrated circuit includes a substrate and a degenerated transistor. The degenerated transistor includes a control terminal formed on the substrate, a channel formed in the substrate beneath the first control terminal, first and second heavily-doped regions embedded in the substrate on opposing sides of the channel, first and second output contacts positioned on the first and second heavily-doped regions, respectively, and a lightly-doped region extending between the first heavily-doped region and the channel. The lightly-doped region has a length that is selected such that the first output contact is spaced from a respective edge of the control terminal by a distance that is at least twice as great as a minimum distance defined for the technology in which the integrated circuit is fabricated and the lightly-doped region has a desired resistance in series with the first output contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.