Semiconductor device having a wire laid between pads
US6621171B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2002 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Jun 17, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
It is intended to lower an increase of an area of an unused area or a wiring area, which is caused due to addition or enhancement of a particular function of a semiconductor device without significantly changing layout of the semiconductor device which has been previously designed. A semiconductor device (100A) has a layout in which a wiring area (102) is surrounded by an extension block (103) as a second semiconductor region and is completely sandwiched between a block (101) and the extension block (103). A plurality of wires (104) are laid across the wiring area (102) only at a single position between two adjacent ones of a plurality of pads (102a) in the wiring area (102), to connect a CPU (201c) in the block (101) and each of a ROM (301), a RAM (302) and an A/D converter (303) in the extension block (103) with each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.