Control circuit for power
US6621299B1 · kind B1 · utility
2Cited by
3References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 4, 2001 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Dec 14, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/003
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit having input output buffers, where the integrated circuit is powered by at least a core power supply and an input output power supply. A level shifter receives an active low signal that indicates that the core power supply has powered down. The level shifter then outputs a known state upon receipt of the active low signal. A control circuit receives the known state form the level shifter, and then tristates the input output buffers upon receipt of the known state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.