High bandwidth multi-phase clock selector with continuous phase output
US6621312B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2001 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Nov 13, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention includes a system and method for improving phase selection using a phase selector system. An exemplary phase selector system of the present invention includes a high speed phase selector having control logic, XOR gates, and a selector. The control logic uses Gray coding to generate one or more control signals. For example, the control logic uses a 3 bit word to select a phase for clock recovery. A selector coupled to the control logic determines the phase selected. XOR gates coupled between the control logic and the selector provide eight phases of a clock using four input phases of the clock with inversion. In this manner, a four to one selector can choose one of eight phases from the XOR gates to aid in clock recovery. The selector control logic has a continuous output phase during a change to an adjacent phase, which substantially prevents glitching on the clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.